1. Field of the Invention
The present invention relates to a read voltage control device for a semiconductor memory device such as a reloadable flash EEPROM or the like.
2. Description of the Prior Art
FIG. 14 is a block diagram showing a conventional read voltage control device for a semiconductor memory device. In the drawing, reference numeral 1 indicates an address bus, reference numeral 2 indicates a data bus, reference numerals 3 and 4 respectively indicate an X decoder and a Y decoder electrically connected to the address bus 1, reference numerals 5 respectively indicate word lines electrically connected to the X decoder 3, reference numerals 6 respectively indicate bit lines electrically connected to the Y decoder 4, and reference numeral 7 indicates a transistor memory (cell) electrically connected to the bit line 6 and the word line 5. A memory cell array comprises a plurality of transistors 7 electrically connected to the lines 5 and 6.
Reference numeral 8 indicates a write pulse generator for generating a write pulse therefrom, which comprises a ring oscillator 9 and a frequency divider 10. Reference numeral 11 indicates a tristate buffer electrically connected to the data bus 2, for blocking the writing of data to a write data latch 12 in response to a write enable signal. Reference numeral 12 indicates the write data latch electrically connected to the tristate buffer 11. Reference numeral 13 indicates a write buffer which comprises transistors 15 and 16 as shown in FIG. 2 and supplies a voltage pulse corresponding to the width of a pulse generated from the write pulse generator 8 from a power supply 14 to the corresponding transistor memory 7 via the Y decoder 4 and the corresponding bit line 6 in response to data outputted from the write data latch 12.
Reference numeral 17 indicates a sense amplifier for reading written data when a read voltage for the corresponding transistor memory 7 rises to a threshold V.sub.TH exceeding a predetermined value. Reference numeral 18 indicates a read data latch electrically connected to the sense amplifier 17. Reference numeral 19 indicates a tristate buffer for blocking the supply of data latched into the read data latch 18 to the data bus 2 in response to a read enable signal. Reference numeral 20 indicates a tester for supplying a new address signal to the X decoder 3 and the Y decoder 4 and supplying a new data signal to the tristate buffer 11 when the tester determines that the data stored in the corresponding transistor memory 7 can be read by the tristate buffer 19 through the data bus 2.
The operation of the read voltage control device will next be explained.
FIG. 14 shows a configuration of a reloadable flash EEPROM. A test to write data into a manufactured flash EEPROM is performed by electrically connecting the tester 20 to the address bus 1 and the data bus 2.
FIG. 15 is a flowchart for explaining the operation of the conventional read voltage control device for a semiconductor memory device. The tester 20 first defines the address as a leading address (Step ST1) and initializes a loop counter X (Step ST2). Next, the tester 20 proceeds to the setting of a program mode (Step ST3) and sets program data and an address (Step ST4).
An address signal outputted from the tester 20 through the address bus I according to the address set in this way, is decoded by the X decoder 3 and the Y decoder 4 so that a given transistor memory 7 of the memory cell array is specified. A data signal outputted from the tester 20 through the data bus 2 in response to the program data set as described above is outputted to the write buffer 13 through the tristate buffer 11 and the write data latch 12. Further, the write buffer 13 supplies a voltage pulse corresponding to the width of the pulse generated from the write pulse generator 8 from the power supply 14 to the above-specified transistor memory 7 through the Y decoder 4 and the corresponding bit line 6. The supply of the voltage to the transistor memory 7 at one time is performed for 10 .mu.s (Step ST5).
Further, the tester 20 increments the loop counter X by 1 (Step ST6) and proceeds to the setting of a program verify mode (Step ST7). The program verify mode is used to read written data when the read voltage for the transistor memory 7 specified by the sense amplifier 17 has risen to the threshold V.sub.TH exceeding the predetermined value and allowing the tester 20 to recognize the satisfactory writing of the specified transistor memory 7 through the read data latch 18, tristate buffer 19 and data bus 2. This program verify mode is executed upon verification (Step ST12). Upon the writing of the data to the transistor memory 7, the supply of the voltage pulse to the transistor memory 7 at one time causes no attainment of the read voltage to the threshold V.sub.TH allowing the reading of the written data and hence the voltage pulse is always supplied plural times. Accordingly, the number of times that the voltage pulse is supplied, is set to 25 times as an upper limit (Step ST9). If the number of times that the voltage pulse is supplied, reaches 25 times and the read voltage fails to reach the threshold V.sub.TH where written data can be read (Step ST10), then the tester 20 sets a read mode and determines the product as a failed component (FAIL) (Step ST11).
If it is determined in Step ST10 that the read voltage has reached the threshold V.sub.TH where written data can be read, then the writing of the data to the transistor memory 7 is determined as satisfactory. If the final address is not reached (Step ST13), then the tester 20 proceeds to the next address (Step ST14). If the answer is found to be NO in Step ST9, then the operations of Steps ST3 to ST12 are repeated until the read voltage reaches the threshold V.sub.TH where written data can be read (Step ST12). Namely, the voltage pulse is supplied to the transistor memory 7 plural times. If the processing on the final address is completed by the repetition of these operations, then the tester 20 sets the read mode and determines the product as a good article (PASS) (Step ST15).
Since the conventional read voltage control device for a semiconductor memory device is constructed as described above, only one type is used as the type of the width of the pulse generated from the write pulse generator 8. Thus, the voltage pulse supplied from the write buffer 13 to the transistor memory 7 has a constant pulse width at all times.
Therefore, the read voltage from the transistor memory 7 rises stepwise as shown in FIG. 16 each time the voltage pulse is supplied from the write buffer 13 to the transistor memory 7. Further, the supply of the voltage pulse from write buffer 13 to the transistor memory 7 is stopped when the read voltage has reached the threshold V.sub.TH at which the sense amplifier 17 can read the written data. However, since the width of the voltage pulse supplied from the write buffer 13 cannot be selected, the width V of the stepwise voltage increases, thus causing a problem that variations in read voltages from the plurality of transistor memories 7 occur.
Further, since the width of the voltage pulse supplied from the write buffer 13 cannot be selected, the number of times that the voltage pulse is supplied to each transistor memory 7 whose read voltage is hard to reach the threshold V.sub.TH exceeding the predetermined value even if the voltage pulse is supplied thereto, increases, thereby causing a problem that time is required to execute a series of tests.
Moreover, there may be cases in which the voltage pulse is simultaneously supplied to the plurality of transistor memories 7. In this case, the difference in the rise of the read voltage occurs between the plurality of transistor memories 7a and 7b due to variations in manufacture as shown in FIG. 17 by way of example. Thus, the voltage pulse is continuously supplied to the transistor memory 7a until the read voltage reaches the threshold V.sub.TH allowing the reading of the data written into the transistor memory 7b. Accordingly, a problem arises in that the difference V in the read voltage is developed between the transistor memories 7a and 7b and an increase in the difference V in the read voltage results in malfunction and makes it hard to execute the subsequent tests.